Typically, a clocking signal used in a digital core is delivered by an on-chip clock generation unit or frequency synthesizer. The clock generation unit may be a Phase Locked Loop (PLL) device, which could also be implemented in the form of a digital PLL. However, such clocking signals may be a source of electromagnetic interference (EMI) to other portions of a system utilizing the digital core. Undesirable electromagnetic energy may propagate throughout the system, or to the external environment, and cause adverse effects to other susceptible devices.
Electromagnetic compatibility (EMC) requirements in various industries, such as the automotive and consumer electronics industries, for example, put stringent limits on the emission of electromagnetic radiation of electronic devices. Accordingly, spread spectrum clocks have been developed for use in digital cores that spread the electromagnetic energy over a wide frequency spectrum, thereby reducing the magnitude of energy at or near a given frequency. A spread spectrum clock may be produced by modulating the output frequency of a PLL, for example, with a low-frequency pattern that “spreads” the energy of the clock signal over a wider bandwidth, effectively reducing the peak spectrum electromagnetic emission.
In some microcontrollers, a single source is typically used to produce the clocks for both the digital core and the low-speed data peripherals. In this scenario, a standard low frequency periodic modulation may not be used, since the accumulated jitter caused by the modulation can exceed the specified jitter limits of the data peripherals, causing transmission to fail. For instance, a 50 kHz triangular modulation with a peak-to-peak modulation amplitude (MA) of 1.5% produces an accumulated jitter of 37.5 ns. Such approaches cannot be used for applications with tight maximum jitter allowances (e.g., 10 ns max jitter).